Many applications require the filtering and subsequent sampling of analog signals. For example, in communications receivers, an analog signal comprising a desired signal, interfering signals, and noise may first be filtered to select the desired signal from among the other undesired signals so that subsequent signal processing may be performed without distortion. Examples of some conventional filters include L-C filters, surface acoustic wave filters, and ceramic filters. Many of these filters are costly, bulky, or difficult to miniaturize. The filters can further lack programmability, which is often desirable. There are other examples of conventional filters that lend themselves to miniaturization in integrated circuits. These include Gm-C filters, MOSFET-C filters, Sallen & Key filters, and others. Many of these consume an unacceptable amount of power or lack the performance required for many applications. Therefore, it would be useful to identify a filter technique that overcomes these conventional limitations.
One technique for filtering and sampling an analog signal is based on sampled correlators as found, for example, in “Principles of Communications Engineering,” by Wozencraft and Jacobs. The system, illustrated in FIG. 1, accepts a received signal “x(t)” 102 that is combined with a correlating signal, “h(t−kT)” 108 using a bilinear analog multiplier 104, where “t” is an increment in time, “k” is an integer, and “T” is a desired sampling interval. The output of the multiplier 104 is filtered and sampled at a periodic interval “kT,” where “k” is an integer and “T” is the desired sampling interval The resulting output signal, “y[k],” 106 is a discrete-time representation of the filtered analog signal.
An advantage of the system illustrated in FIG. 1 is that filtering and sampling is performed computationally with components that are readily miniaturized. However, the system is not without disadvantages. For example, it is sometimes difficult to build an accurate analog multiplier 104. Without an accurate analog multiplier 104, the performance of this system is often limited. One technique for building analog multipliers is taught by Gilbert in “A Precise Four-Quadrant Multiplier with Subnanosecond Response.” However, Gilbert's technique lacks the necessary accuracy for many applications.
The difficulty of building analog multipliers is also recognized in other publications and other United States and European Patents. U.S. Pat. No. 3,953,795 to Brunner, for example, discloses an electric power meter implementing an analog multiplier using a commutating mixer driven by a two-level pulse width modulator. Eynde, in “A Power Metering ASIC with a Sigma-Delta-Based Multiplying ADC,” discloses an electric power meter with a commutating mixer which uses a special type of pulse width modulator. Eynde's structure is substantially disclosed in European Patent Off. No. 589,090. U.S. Pat. No. 5,862,069 to Nestler, eliminates analog multiplication problems by performing multiplication in the digital domain after modulating both input signals. Accordingly, there is a need for an apparatus and method that can produce accurate correlation and, hence, filtering of an analog signal in a manner that lends itself to miniaturization within integrated circuits.